Over the past decade, constant innovations in silicon processing technology have drastically reduced the price and increased the performance and functionality of integrated circuit devices. As a result, industries are increasingly demanding integrated circuit design systems. Chip designs are therefore becoming larger and more complex and more application-specific.
With the increased demand from industry, electronics product development has become partially consumer driven, resulting in a shortened product life cycle. Thus, consumer demand has placed downward pressure on design time, and design managers increasingly are required to make crucial design decisions or predictions prior to some system component designs being complete.
Generally, a designer of a large-scale digital system begins with a high-level (abstract) idea of the tasks the system is to perform. To realize the system in some physical technology, such as a collection of integrated circuits, the designer determines how to implement the system through the interconnection of millions of transistors to perform the desired operations. The need to translate from a high-level conceptual view of the system to a specification of the complex interconnections among the millions of transistors is sometimes called the “abstraction gap”.
To address the design time constraints and the predictive pressures placed on design managers, and to close this abstraction gap, electronic system design has moved toward a methodology referred to in the art as “block-based design”. The block-based design methodology is a range of techniques that take advantage of existing component design blocks, which have been designed and tested previously. Such design blocks can be integrated into larger integrated circuit designs or into subsystems to perform various functions. These blocks are sometimes referred to as intellectual property blocks or IP blocks.
Conventional integrated circuit design methodologies are not well-suited for reuse of pre-designed circuit blocks. Without a comprehensive approach to block reuse, existing methodologies cause ad hoc and unpredictable design results, reduce design realization feasibility, and increase cost and time to delivery. Moreover, use of such blocks can trigger performance degradation to the blocks themselves and to the larger circuit.
Theoretically, reusable intellectual property or reusable IP can significantly reduce development time. Specifically, reusable IP should theoretically be reusable in the same manner on different chips, thereby reducing design time in terms of developing functional or logical elements to perform the same functions.
In general, there are two industry standard hardware description languages for electronic design and gate-level simulation for use in designing and generating integrated circuits. The two description languages are Verilog and VHDL (“Very High Speed Integrated Circuit (VHSIC) Hardware Description Language”). A hardware description language, such as Verilog, is used by a designer to model new integrated circuit designs. Verilog, for example, allows the engineer to represent the desired functionality as a software program. The model may then simulated on a computer to see if the design will work as intended. Problems can be corrected in the model and verified in simulation. Finally, the verified hardware description code can be synthesized into an integrated circuit.
The Verilog hardware description language was first introduced in 1984, as a proprietary language from Gateway Design Automation. In 1989, Gateway Design Automation was acquired by Cadence Design Systems, which released the Verilog hardware description language in the Verilog programming language interface to the public domain in 1990. Open Verilog International was formed to control the public domain Verilog, and to promote its usage. In 1993, Open Verilog International submitted a request to the IEEE to formally standardize Verilog 2.0. The IEEE formed a standards working group to create the standard, and, in 1995, IEEE adopt the Verilog standard as IEEE 1364-1995.
The IEEE 1364-1995 Verilog standard provided a significant step forward in terms of integrated circuit design and standardization of hardware description language protocols. However, the 1995 Verilog standard presented a problem with respect to multiple instantiations of configurable intellectual property in an integrated circuit design. In particular, multiple instantiations of intellectual property in a design, where different configurations are used for each instantiation, required special handling. Specifically, in order to handle multiple instantiations of a configurable peripheral or IP block in a chip design, the conventional flow required “uniquefying” or uniquely naming each peripheral instantiation so that they could co-exist with the same design.
Within software, multiple instantiations required header files to find register addresses which were renamed to co-exist. In other words, header files/C code were duplicated and renamed. Unfortunately, renaming the peripheral instantiations required the Register Transfer Level code (RTL) to be modified after verification, potentially introducing errors in the design. Additionally, duplicating and renaming header files required significant coding and debugging time. If the peripheral instantiation is renamed after verification, the uniquified RTL code should be verified to ensure that it is equivalent to the original RTL code. Both dynamic (simulation) and static (equivalence checking) may be used to verify the peripheral device. However, such a secondary verification process would take away some of the time-to-market benefits of reusable peripheral instantiations.
In general, it can often seem that designing integrated circuits is similar to writing a piece of software. Both the behavior and structural models of integrated circuit elements are written in the hardware description language, and can be changed, compiled, and simulated in a manner similar to writing, compiling and executing a program written in a high-level programming language, such as Java or C++, for example. However, the two processes are fundamentally different.
A hardware designer generally begins with a Functional Design Description (FDD), which provides the abstract descriptions of the functions the system will be capable of performing. The designer develops a functional and behavioral model, refines the model, and synthesizes the model into a structural model (i.e. a gate-level netlist). The gate-level netlist is then processed to generate the masks for an integrated circuit. The resulting integrated circuit consists of hardware storage elements for the FDD-defined registers, logic circuits that implement the FDD-specified instructions, and a memory system. In the final result, the integrated circuit is a physical chip (a piece of hardware). To change the processor, for example to add an instruction, every step in the chain of events must be repeated, and the resulting chip has additional logic circuits necessary to implement the new instruction. By contrast, a software developer writes and compiles the code into a software executable that resides in memory on a computer. A change in the code requires the designer to add lines of code, to recompile the revised code, and to store the recompiled code again.